This invention relates to digital in-circuit testers for testing newly-built printed circuit assemblies. Testers usually have a central processing unit, a testhead controller, one or more driver-receiver cards, and channels. The channels are used to either drive a printed circuit assembly test node or receive a signal from that node, or both drive and receive signals. A small in-circuit tester may be equipped with up to about two hundred channels, and can test small boards. Large digital in-circuit testers with more than three thousand channels also exist. Typical digital in-circuit testers are disclosed in the following patents: U.S. Pat. Nos. 4,339,819 to Jacobsen; 4,216,539 to Raymond et al.; 3,943,439 to Raymond; and 3,931,506 to Borrelli et al. These patents are incorporated herein by reference.
A test-head controller is a complex piece of electronic circuitry which performs many tasks in an in-circuit tester. The test-head controller is often the primary interface between the central processing unit and the rest of the electronic circuits in the tester. In many testers, the test-head controller's list of functions may include control of vacuum valves for fixture actuation, interaction with operator controls and displays, and many other necessary jobs.
An important function of the test-head controller is to control the operation of the driver-receiver cards; that is, assisting them in setting up and executing a burst of test vectors. A "test vector" is a snapshot in time of the state of all the terminals of a device under test ("DUT"). A "burst" is an ordered sequence of vectors intended to conduct a test of the DUT.
Usually the CPU sends information describing a burst to the test head controller, and then the test head controller runs the burst.
The test burst produced by the action of the test head controller is much faster than would be possible were there a small computer organizing the progress of the burst from one vector to the next. Typical computer instruction cycle times are on the order of five hundred to one thousand nanoseconds, and several instructions might be required to get the computer to move from one vector to the next. Thus, the amount of time required to get from one vector to the next in a computer-drive sequence might be more in the neighborhood of five to ten microseconds. A typical test-head controller-based system generates the vectors with special parallel vector-generating hardware capable of delivering a new vector every twenty to five hundred nanoseconds, which is three or more orders of magnitude faster than if a small computer controlled the test vector bursts.
In prior art in-circuit testers, it is common for every terminal of the DUT to be driven and sensed as needed at appropriate occasions during a given test burst.
Commonly in prior-art in-circuit testers, every channel circuit is equipped with a local memory ("RAM"). The memory contains some encoded representation of the sequence of states the channel will go through during the burst. The speed of the memory is often the governing factor in the speed of a test vector burst. If the memory cannot be read but once every one hundred nanoseconds, for example, the driver may not change its state more often than that. Speed is desirable for two reasons. First, devices which pass tests at slow vector burst rates are known to be capable of failing at higher rates. Thus, a faster burst-rate tester is a more effective detector of bad devices. Second, digital in-circuit testers are used in high-production-rate factories, and cannot be allowed to bottleneck vital product flows by consuming time.
Typically, the memories are read out much faster than they are written into. The memories are all read out in parallel during a burst, but the CPU must load them up individually before it can ask the test-head controller to run the burst. Also, prior to the running of the burst, the CPU must execute several instructions for each word of information the CPU transfers to a memory.
Digital in-circuit testers owe their well-known test and diagnostic power to their practice of testing a printed circuit assembly one component at a time. In order to test a single component in a printed circuit assembly, a tester must apply signals directly to its inputs and measure the signals which emanate from its outputs. In particular, and in the idealized case, the tester must pretend that there are no neighboring components generating spurious signals to interfere with the application of the tester's carefully-crafted test vectors. If a neighboring component changes state at an inopportune time, the signal coming from its output may cause noise to superimpose on the signals coming from the tester, and cause an erroneous result.
In-circuit testers attempt to cope with the neighboring-component problem by providing their signals through drivers having very low impedance. Typical in-circuit drivers can drive normal logic voltage levels while sourcing or sinking over four hundred milliamperes. This is called "backdriving" in the test equipment industry. This amount of current is enough to overcome the somewhat higher impedances of the outputs of neighboring components. It is not a complete solution to the problem, however. Some outputs of a printed circuit assembly are actually capable of overcoming a typical in-circuit driver, and other outputs have voluntary signals (e.g. free-running clock oscillators) which cause short-wavelength spikes to leak through the DC backdrive signal.
In any given printed circuit assembly, there is a group of identifiable points which when programmed to the proper state will silence oscillators, and "disable" all data buses. The list is not the same from one printed circuit assembly to another, so it is useful to recognize this property in general and provide for it in the tester's programming system. It is common practice in in-circuit testing to list such points at the beginning of the program in a software construct that will cause the points to be included in every subsequent test burst (programmed to the proper state) whether specifically programmed for that burst or not.
Because the purpose of programming this list of points is to "disable" devices on the DUT which could interfere with the test bursts, the list is commonly referred to as the "disable table". It allows the test programmer to establish a background state in which a DUT is disabled; all subsequent vector bursts in the program will be superimposed on this background state. This saves programming and debugging efforts, by affording the programmer a way to deal with the interference subject just once, and thus not having to acknowledge and work around the problem again on each test of the DUT.
The software system which provides this service of establishing a background state now has an important management job to perform. For each burst, the software must consider whether or not (1) any of the points to be measured are involved in the disable table, and (2) any of the points to be stimulated are involved in the disable table.
Obviously, if a particular test needs to measure a particular output and that output is being backdriven to a steady state because of the disable table entry, the measured signal would not yield a correct response. The tester must remove the entry temporarily from the disable table.
Also, if a particular test needs to stimulate a point which happens to be in the disable table, the disable table must again be temporarily modified so as to apply the desired stimulus rather than the disabling background state. After each burst, the disable table must be returned to its "normal" state.
Clearly, it would be beneficial to decrease the amount of time spent modifying and returning to normal the disable table. Also, it would be beneficial to decrease the amount of time spent loading up the channel memories between bursts of test vectors.
Prior art attempts at this include: increasing the speed of the download hardware, e.g. with direct-memory-access (DMA) hardware in the computer; partitioning the channel memory so that one download can serve for many different bursts; improving the efficiency of the code which describes the vectors to be generated, so that long strings of bits can be regenerated from a small amount of downloaded information; and improving the structure of the memory so that operations such as "erase" which affect multiple cells in the memory can be accomplished in a single event.
The present invention simplifies the CPU's job of modifying the disable table and reloading the channel memories with encoded information for the next burst. Thus, the present invention contributes to the speed of reprogramming between bursts. The present invention protects the contents of the memories of preselected channel circuits associated with the disable table, from being erased whenever the stimulus required for the test sequence is erased.